library verilog;
use verilog.vl_types.all;
entity mux4_to_1 is
    port(
        enable          : in     vl_logic;
        input_1         : in     vl_logic;
        input_2         : in     vl_logic;
        input_3         : in     vl_logic;
        input_4         : in     vl_logic;
        s1              : in     vl_logic;
        s2              : in     vl_logic;
        output_data     : out    vl_logic
    );
end mux4_to_1;
